1. Field of the Invention
The present invention relates to a bus control apparatus and a bus control method, and more particularly, to a bus control apparatus including one or more blocks configured to output a write command signal for writing data into memory via a bus, and a bus control method.
2. Description of the Related Art
There have been known apparatuses in which data is transmitted/received between functional blocks via a bus. For example, in recent apparatuses, a number of blocks on a System-on-Chip (SoC) transmit/receive data to and from each other by way of a system bus and via shared memory that is connected to the chip.
By way of example, when a block A is to transfer data to another block B, the block A transfers and writes the data to shared memory, and when the data transfer is finished, the block A notifies the block B of the completion of data transfer. The block B can then read the data from the block A by transferring the data from a storage area of the shared memory in which the data is written.
Due to a necessity of data consistency, it is a precondition for data transfer in such a shared-memory configuration that operations at each phase of data transfer must be completed before processing for a next phase takes place. The bus on which data is transmitted/received may be a shared bus or a point-to-point bus.
Meanwhile, many of modern bus architectures use a bus protocol which adopts a posted write scheme as a standard way of writing to a bus in order to improve bus efficiency. In the posted write scheme, when a block writes to shared memory, the block considers writing to be completed at a point when the block has finished passing a write command and data to be written to a bus. The data will be actually written to the memory when the bus and the memory (including a controller) are ready for writing.
However, some attention needs to be paid when data is exchanged according to such a procedure on a bus that uses the posted write scheme. It is a problem of memory consistency or coherency, which means correct read data cannot be retrieved unless reading by the other block B is carried out after the posted write reaches the shared memory.
General ways for maintaining data coherency include methods based on a bus protocol, hardware (hereinafter also abbreviated as HW) implementation, software (hereinafter also abbreviated as SW) implementation, or some combination of SW and HW implementations, which are already realized.
Some methods based on a bus protocol use non-posted write for a write that is used in common with other blocks.
However, a bus protocol-based method has a problem of involving complex HW implementation for executing the protocol. In general, implementation of non-posted write is more complex than that of posted write. In addition, performance of HW, especially throughput and overhead in terms of operating frequency, may present a problem.
For hardware implementation-based methods, there is an address interlocking technique, which identifies dependencies among all write and read addresses and makes reading wait as required. For example, a read from an address which is not related to an address at which data was written needs not to be made to wait, whereas a read from an address which is related to an address at which data was written needs to be made to wait. The address interlocking technique thus identifies a dependency between write and read addresses and decides whether or not to make a read wait.
However, a problem with methods based on HW implementation is that HW implementation is complex. Moreover, most portions of general shared buses are not typically involved in transaction between separate blocks. Therefore, application of address interlocking in every transaction can present a problem in terms of performance, especially throughput and operating frequency.
Japanese Patent Laid-Open No. 2002-82901 proposes a technique for a software implementation-based method in which a block as a data source issues a dummy read after a data write in order to confirm the write. This proposed technique presupposes a bus protocol using the posted write scheme with a restriction that when a read is issued by a same block, any write before the issuance must be completed.
However, methods based on software implementation generally have a problem of processing being sometimes extremely complex. Because of this fact, when a vendor supplying SoC chips leaves software implementation to a customer, for example, the customer might not be able to accept software implementation that involves such complex processing.